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sdram
- 在ISE环境中，利用verilog语言编写的SDRAM的控制，已经通过功能仿真，其中PLL部分并没有加入，使用时可以自行加入PLL模块。-Verilog language in the ISE environment, the use of SDRAM control, through functional simulation, which the PLL part and did not join, can join the PLL blocks.
VCO
- 压控振荡器的FPGA实现，Verilog语言完成。编译环境 ISE 13.2-The vco FPGA realizing, Verilog language completed. Compile environment ISE 13.2
comparator
- 使用verilog语言，在FPGA开发工具ISE上实现比较器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the comparator function.
flip_flop
- 使用verilog语言，在FPGA开发工具ISE上实现触发器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the flip-flop function.
lcd
- lcd 1602 verilog ise xilinx-the lcd 1602 Verilog ise xilinx
mux16
- mux 乘法器 verilog ise xilinx-the mux multiplier Verilog ise xilinx
Viterbi11111
- 使用Verilog编写的vertbi译码模块，ISE12.2下编译通过，主用是调用ISE下的Vertibi核设计实现的。-Written using Verilog vertbi decoding module, ISE12.2 compiled by the main use is to call ISE the nuclear Vertibi designed to achieve.
ttraafficLighr
- <p>交通灯状态机的实现，用verilog HDL编程与开发，Xillinx ISE 6仿真，在实际电路中的到验证． 已通过测试。</p> -<p> The implementation of the traffic light state machine, using verilog HDL programming and development, Xillinx ISE 6 simulation, to verify the actual circui
lms
- 文件中为lms算法的ise工程，其中包含了lms算法的fpga实现的verilog程序以及testbench，很好的在FPGA上实现了lms算法，还有一些调试程序的总结-Ise project file for lms algorithm, which contains the lms algorithm fpga verilog program to achieve and testbench good lms algorithm implemented on FPGA debugger su
verilog_UART_100MHZ
- 自己写的verilog UART程序，前仿真后仿真，下到板子里都对，ISE的-Verilog UART write your own program, before simulation after simulation, are right next to the plate yard, ISE' s
Mstateei
- 米勒解码器的状态转换模块。用verilog语言编写写，ISE为开发环境 ，经测试可直接使用。 -Miller decoder state transition module. Verilog language writing, ISE development environment has been tested and can be used directly.
calculator
- 基于赛灵思的spartan-3e开发板的语音智能计算器的设计，开发语言verilog，开发软件ISE，可以根据ucf文件理清引脚关系。应用者需要对开发板和fpga设计有一定的了解！-Development board based on Xilinx spartan-3e voice smart calculator design, development languages Verilog, developing software ISE, according to
mips--cpu
- 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic de
frequency
- 能够检测方波正弦波以及锯齿波的频率，并且以及试过可以运行，采用的开发环境是ISE，编程语言是Verilog-Able to detect a square wave frequency of the sine wave and sawtooth wave, and as well tried can run the development environment is the ISE, the programming language is Verilog
RS232
- RS232与电脑串口的通信控制代码，verilog hdl代码，里面包括完整的ISE工程-RS232 and computer serial communication control code, verilog hdl code, which includes a complete ISE works
hdb3
- 该代码使用Verilog HDL语言编写的，能够对HDB3码进行编译，该文件是完整的，可以直接在ISE软件上运行-Compile the code using Verilog HDL language, HDB3 code, the file is complete, you can run directly in the ISE software
a1
- 1 bit MUX 用ISE写的1bit MUX的verilog code 可以在ISE上模拟1bit MUX的运作-1 bit MUX It is a file of verilog code to design a 1 bit MUX. It is design by ISEbit
Useful_data
- Full flow descr iption of the flow of developing the verilog code in ISE and steps in implementing and executing in fpga
ImageRotate
- 利用verilog实现图像旋转。本程序是基于XILINX公司的ISE实现的。-Verilog image rotation. This procedure is based on XILINX' s ISE.
carry_select
- 上传的代码是基于Xilinx下的ISE开发平台，用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.